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 EMIF06-1005M12
6-line IPADTM
low capacitance EMI filter and ESD protection in micro QFN package Features

12 11 10 9 8 7
GND
1 2 3 4 5 6
EMI symmetrical (I/O) low-pass filter High efficiency in EMI filtering: -34 dB at frequencies from 900 MHz to 1.8 GHz Very low PCB space consumption: 2.5 mm x 1.5 mm Very thin package: 0.6 mm max High efficiency in ESD suppression on inputs pins (IEC 61000-4-2 level 4) High reliability offered by monolithic integration High reduction of parasitic elements through integration and wafer level packaging Lead-free package
2 Input
Micro QFN 2.5 mm x 1.5 mm (bottom view)
Figure 1.
Pin configuration (top view)
Output 12
1 Input
Output 11
Complies with following standards:
IEC 61000-4-2 level 4 input and output pins - 15 kV (air discharge) - 8 kV (contact discharge) MIL STD 883G - Method 3015-7 Class 3B (all pins)
3 Input
Output 10
4 Input
Output 9
5 Input
Output 8
Applications
Where EMI filtering in ESD sensitive equipment is required:

6 Input
Output 7
LCD and camera for mobile phones Computers and printers Communication systems MCU boards
Figure 2.
Input
Basic cell configuration
100 Output
Description
EMIF06-1005M12 is a 6-line, highly integrated device designed to suppress EMI/RFI noise in all systems exposed to electromagnetic interference. This filter includes ESD protection circuitry, which prevents damage to the application when subjected to ESD surges up to 15 kV on the input pins.
Typical line capacitance = 45 pF @ 0 V
TM: IPAD is a trademark of STMicroelectronics
February 2008
Rev 3
1/10
www.st.com
Characteristics
EMIF06-1005M12
1
Table 1.
Symbol VPP Tj Top Tstg
Characteristics
Absolute ratings (limiting values at Tamb = 25 C unless otherwise specified)
Parameter ESD IEC 61000-4-2, air discharge ESD IEC 61000-4-2, contact discharge Junction temperature Operating temperature range Storage temperature range Value 15 15 125 -40 to + 85 -55 to +150 Unit kV C C C
Table 2.
Symbol VBR IRM VRM VCL Rd IPP RI/O Cline
Electrical characteristics (Tamb = 25 C)
Parameter Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic resistance Peak pulse current Series resistance between Input & Output Input capacitance per line Test conditions IR = 1 mA IF = 10 mA VRM = 3 V per line Tolerance 10% VLINE = 0 V dc, VOSC = 30 mV, F = 1 MHz 90 38 100 45 Min. 6 0.5 Typ. 8 1.0 Max. 10 1.5 200 110 52 nA pF Unit V
IPP VBR VCL VRM IRM IR VF V I IF
Symbol VBR VF IRM RI/O Cline
Figure 3.
0.00
S21 attenuation measurement
dB
Figure 4.
0.00 - 10.00 - 20.00
Analog cross talk measurements
dB
-10.00
- 30.00 - 40.00
-20.00
- 50.00 - 60.00
-30.00
- 70.00 - 80.00
F (Hz)
-40.00 100.0k 1.0M 10.0M 100.0M 1.0G
- 90.00 - 100.00 1.0M 3.0M
F (Hz)
10.0M 30.0M 100.0M 300.0M 1.0G 3.0G
2/10
EMIF06-1005M12
Ordering information scheme
Figure 5.
ESD response to IEC 61000-4-2 Figure 6. (+15 kV air discharge) on one input (Vin) and on one output (Vout)
ESD response to IEC 61000-4-2 (- 15 kV air discharge) on one input (Vin) and on one output (Vout)
Figure 7.
Line capacitance versus reverse voltage applied (typical value)
(pF) C 50.00 LINE 45.00 40.00 35.00 30.00 25.00 20.00 15.00 10.00 5.00 0.00 0
V LINE (V) 1 2 3 4 5
2
Ordering information scheme
Figure 8. Ordering information scheme
EMIF
EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) Package Mx = Micro QFN x leads
yy
-
xxx z
Mx
3/10
Package information
EMIF06-1005M12
3
Package information
Epoxy meets UL94, V0
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Table 3. QFN 2.5 x 1.5 package dimensions
D
N
Dimensions Ref
E
Millimeters MIN TYP 0.55 0.02 0.18 2.50 1.70 1.80 1.50 0.30 0.40 0.40 0.20 0.25 0.30 0.35 0.08 0.10 0.50 0.12 1.90 0.67 MAX 0.60 0.05 0.25 MIN 0.20 0.00 0.06
inches TYP 0.22 0.01 0.07 0.98 0.71 0.59 0.16 0.16 0.24 0.75 MAX 0.24 0.02 0.10
A
1 2
0.50 0.00 0.15
A1
A A1 D2
1 2
b D D2
L
E E2
E2 k
N
e k L
b e
0.12
0.14
Figure 9.
Footprint
0.40
Figure 10. Marking
0.20
0.60 0.25 0.40 2.10
Dot: Pin 1 Identification X = Marking YWW= Data code (Y=year WW= week
XY ww
1.80
4/10
EMIF06-1005M12 Figure 11. Tape and reel specification
2.0+/-0.05 4.00+/-0.1
Package information
f 1.5 +/- 0.1
1.75 +/- 0.1 3.5 +/- 0.05
0.75
8.1 +/- 0.1
XY ww
XY ww
XY ww
2.70
1.70 User direction of unreeling
4.00
Note:
Product marking may be rotated by 90 for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose.
5/10
Recommendation on PCB assembly
EMIF06-1005M12
4
4.1
Recommendation on PCB assembly
Stencil opening design
1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 12. Stencil opening dimensions
L
T
W
b)
General design rule Stencil thickness (T) = 75 ~ 125 m W Aspect Ratio = ---- 1.5 T LxW Aspect Area = --------------------------- 0.66 2T ( L + W )
2.
Reference design a) b) c) Stencil opening thickness: 100 m Stencil opening for central exposed pad: Opening to footprint ratio is 50%. Stencil opening for leads: Opening to footprint ratio is 90%.
Figure 13. Recommended stencil window position
5 m 5 m 15 m
600 m
570 m
0.40
0.20
0.60 190 m 15 m 0.40 200 m 2.10 0.25
1800 m 50 m 300 m 1.80
400 m
1224 m 50 m 288 m
Footprint
Stencil window Footprint
288 m
6/10
EMIF06-1005M12
Recommendation on PCB assembly
4.2
Solder paste
1. 2. 3. 4. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. "No clean" solder paste is recommended. Offers a high tack force to resist component movement during high speed Solder paste with fine particles: powder particle size is 20-45 m.
4.3
Placement
1. 2. 3. 4. Manual positioning is not recommended. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering Standard tolerance of 0.05 mm is recommended. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
5. 6.
4.4
PCB design preference
1. 2. To control the solder paste amount, the closed via is recommended instead of open vias. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
7/10
Recommendation on PCB assembly
EMIF06-1005M12
4.5
Reflow profile
Figure 14. ST ECOPACK(R) recommended soldering reflow profile for PCB mounting
Temperature (C)
260C max 255C 220C 180C 125 C
2C/s recommended 2C/s recommended 6C/s max 6C/s max
3C/s max 3C/s max
0 0 1 2 3 4 5
10-30 sec 90 to 150 sec 90 sec max
6
7
Time (min)
Note:
Minimize air convection currents in the reflow oven to avoid component movement.
8/10
EMIF06-1005M12
Ordering information
5
Ordering information
Table 4. Ordering information
Marking F(1) Package Micro QFN Weight 6 mg Base qty 3000 Delivery mode Tape and reel (7")
Order code EMIF06-1005M12
1. The marking can be rotated by 90 to differentiate assembly location
6
Revision history
Table 5.
Date 3-Jul-2006 1-Feb-2007 04-Feb-2008
Document revision history
Revision 1 2 3 Initial release. Added note on marking rotation in section 3. Package information. Reformatted to current standards. Updated ECOPACK statement. Updated Section 4: Recommendation on PCB assembly. Changes
9/10
EMIF06-1005M12
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
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10/10


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